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FEATURES Optimally Compensated Active Voltage Positioning with Gain and Offset Adjustment (ADOPTTM) for Superior Load Transient Response Complies with VRM 8.5 Specifications with Lowest System Cost 5-Bit Digitally Programmable 1.05 V to 1.825 V Output N-Channel Synchronous Buck Controller Onboard 1.8 V Linear Regulator Controller Total Accuracy 1% Over Temperature High Efficiency Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components APPLICATIONS Core and 1.8 V Standby Supplies for Next Generation Intel Pentium(R) III Processors
SD
VRM 8.5 Compatible Single Phase Core Controller ADP3170
FUNCTIONAL BLOCK DIAGRAM
VCC CT SET RESET CROWBAR 3.0V REFERENCE GND REF 1.8V LRFB LRDRV CS- CMP CS+ FB COMP REF VID DAC gm DAC -20% REF DAC +20% PWRGD PWM LOGIC UVLO AND BIAS OSCILLATOR DRVH DRVL PGND
ADP3170
VID3 VID2 VID1 VID0 VID25
GENERAL DESCRIPTION
The ADP3170 is a highly efficient output synchronous buck switching regulator controller optimized for converting a 5 V main supply into the core supply voltage required by next generation Intel Celeron processors. The ADP3170 uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 1.05 V and 1.825 V. The ADP3170 uses a current mode, constant off-time architecture to drive two N-channel MOSFETs at a programmable switching frequency that can be optimized for regulator size and efficiency. The ADP3170 also uses a unique supplemental regulation technique called Analog Devices Optimal Positioning Technology (ADOPT) to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard currentADOPT is a trademark of Analog Devices, Inc. Pentium is a registered trademark of Intel Corporation
mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3170 also provides accurate and reliable short circuit protection and adjustable current limiting. It also includes an integrated overvoltage crowbar function to protect the microprocessor from destruction in case the core supply exceeds the nominal programmed voltage by more than 20%. The ADP3170 contains a 1.8 V linear regulator controller that is designed to drive an external N-channel MOSFET. This linear regulator can be used to generate auxiliary voltages (such as 1.8 V standby power) required in most motherboard designs, and has been designed to provide a high bandwidth load-transient response. The ADP3170 is specified over the commercial temperature range of 0C to 70C and is available in a 20-lead TSSOP package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
ADP3170-SPECIFICATIONS1
Parameter FEEDBACK INPUT Output Accuracy 1.05 V Output 1.5 V Output 1.825 V Output Line Regulation Input Bias Current Crowbar Trip Point Crowbar Reset Point Crowbar Response Time REFERENCE Output Voltage Output Current VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-up Resistance Internal Pull-up Voltage SHUTDOWN INPUT Input Low Voltage Input High Voltage Input Current OSCILLATOR Off Time CT Charge Current ERROR AMPLIFIER Output Resistance Transconductance Output Current Maximum Output Voltage Output Disable Threshold -3 dB Bandwidth CURRENT SENSE Threshold Voltage Symbol VFB
(VCC = 12 V, IREF = 150 A, TA = 0 C to 70 C, unless otherwise noted.)
Min Typ Max Unit
Conditions
VOUT IFB VCROWBAR tCROWBAR VREF IREF VIL(VID) VIH(VID) IVID RVID
Figure 1 Figure 1 Figure 1 VCC = 10 V to 14 V % of Nominal DAC Voltage % of Nominal DAC Voltage Overvoltage to DRVL Going High
1.039 1.485 1.807
115 40
1.05 1.5 1.825 0.06 5 120 50 400 3.0
1.061 1.515 1.843 50 125 60
V V V % nA % % ns V A V V A k V V V A s A A M mmho A V mV kHz mV mV mV A ns
2.937 300
3.048
0.8 2.3 VID(X) = 0 V 2.75 300 16 3.1 425 3.4 0.8 2.0 1 TA = 25C, CT = 200 pF TA = 25C, VOUT in Regulation TA = 25C, VOUT = 0 V 3.5 130 25 4.0 150 35 1 2.2 625 3.0 750 500 78 45 1 0.5 50 4.5 170 45
VIL(SD) VIH(SD) ISD
ICT
RO(ERR) gm(ERR) IO(ERR) VCOMP(MAX) VCOMP(OFF) BWERR VCS(TH) ICS+, ICS- tCS
2.05 FB = 0 FB Forced to VOUT - 3% 600 COMP = Open FB Forced to VOUT - 3% FB 0.45 V 0.8 V COMP 1 V CS+ = CS- = VOUT CS+ - (CS-) > 87 mV to DRVH going low IL = 50 mA CL = 3000 pF 69 35
2.35
900
Input Bias Current Response Time OUTPUT DRIVERS Output Resistance Output Transition Time LINEAR REGULATOR Feedback Current LR Feedback Voltage Driver Output Voltage
87 54 5 5
RO(DRV[X]) t R , tF ILRFB VLRFB VLRDRV
4.5 75 0.3 1.8 1 1.85
ns A V V
Figure 2, VCC = 4.5 V to 12.6 V VCC = 4.5 V, VLRFB(X) = 0 V
1.75 4.2
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Parameter POWER GOOD COMPARATOR Undervoltage Threshold Undervoltage Hysteresis Overvoltage Threshold Overvoltage Reset Point Output Voltage Low Response Time SUPPLY DC Supply Current2 UVLO Threshold Voltage UVLO Hysteresis Symbol VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) Conditions % of Nominal DAC Voltage % of Nominal DAC Voltage % of Nominal DAC Voltage % of Nominal DAC Voltage IPWRGD(SINK) = 1 mA Min 74 114 40 Typ 80 5 120 50 250 200 7.5 7 1 Max 86 126 60 500 Unit % % % % mV ns mA V V
ICC VUVLO
6.75 0.8
9.5 7.25 1.2
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +15 V DRVH, DRVL, LRDRV . . . . . . . . . . -0.3 V to VCC + 0.3 V All Other Inputs & Outputs . . . . . . . . . . . . . . -0.3 V to +10 V Operating Ambient Temperature Range . . . . . . . 0C to 70C Operating Junction Temperature . . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND.
ORDERING GUIDE
Model
ADP3170JRU
Temperature Range
0C to 70C
Package Description
TSSOP
Package Option
RU-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3170 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN CONFIGURATION RU-20
VID3 1 VID2 2 VID1 3 VID0 4 VID25 5 PWRGD 6
20 19 18 17
GND PGND DRVH DRVL VCC
ADP3170
16
TOP VIEW 15 LRFB (Not to Scale) 7 14 LRDRV REF SD 8 FB CS-
9 10 13 12 11
COMP CT CS+
PIN FUNCTION DESCRIPTIONS
Pin No. 1-5
Mnemonic VID3, VID2, VID1, VID0, VID25 PWRGD REF SD FB CS- CS+ CT COMP LRDRV LRFB VCC DRVL DRVH PGND GND
Function Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a logic one if left open. The DAC output programs the FB regulation voltage from 1.05 V to 1.825 V. Open drain output that signals when the output voltage is in the proper operating range. 3.0 V Reference Output. Regulator Shutdown. Pulling this pin high turns off both MOSFETs of the switching regulator. SD has no effect on the linear regulator controller. Feedback Input. Error amplifier input for remote sensing of the output voltage. Current Sense Negative Node. Negative input for the current comparator. Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS-. External capacitor connected from CT to ground sets the OFF-Time of the device. Error Amplifier Output and Compensation Point. The voltage at this output programs the output current control level between CS+ and CS-. Gate Drive for the 1.8 V linear regulator N-channel MOSFET. Feedback Connections for the 1.8 V linear regulator controller. Supply Voltage for the ADP3170. Low-Side MOSFET Drive. Gate drive for the synchronous rectifier N-channel MOSFET. The voltage at DRVL swings from GND to VCC. High-Side MOSFET Drive. Gate drive for the buck switch N-channel MOSFET. The voltage at DRVH swings from GND to VCC. Power Ground. PGND should have a low impedance path to the source of the synchronous MOSFET. Small-Signal Ground. This ground reference can be used in conjunction with FB to provide remote sensing of the output voltage at the CPU pins.
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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ADP3170
1 2
VID3 VID2 VID1 VID0 VID25 PWRGD REF SD FB CS-
GND 20 PGND 19 DRVH 18 DRVL 17 VCC 16 LRFB 15 LRDRV 14 COMP 13 CT 12 CS+ 11 AD820
9 1
5-BIT CODE
3 4 5 6 7 8
ADP3170
VID3 VID2 VID1 VID0 VID25 PWRGD REF SD FB CS- GND 20 PGND 19 DRVH 18 DRVL 17 VCC 16 LRFB 15 LRDRV 14 COMP 13 CT 12 CS+ 11 10nF VLR 1F VCC 100nF
12V 1F 100nF
2 3 4 5
VFB
9 10
100 100nF
6 7 8
1.2V
10
Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit
Figure 2. Linear Regulator Output Voltage Accuracy Test Circuit
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ADP3170-Typical Performance Characteristics
100 TA = 25 C 80
SUPPLY CURRENT - mA
TEK RUN TRIG'D
60
VCC
1
40
20
VCORE
2
0
0
100
200 300 400 SWITHCHING FREQUENCY - kHz
500
CH1 5.00V BW CH2
500mV BW M 10.0ms A CH1 0.00000 s
5.90V
TPC 1. Supply Current vs. Operating Frequency Using MOSFETs of Figure 3
25
T
TPC 4. Power-On Start-Up Waveform
TA = 25 C VOUT = 1.5V 20
NUMBER OF PARTS - %
15
1
10
5
2
0
CH1 5.00V BW CH2 5.00V BWM 400ns A CH1 6.60V
-0.6
0 OUTPUT ACCURACY - % OF NOMINAL
0.6
TPC 2. Gate Switching Waveforms Using MOSFETs of Figure 3
TPC 5. Output Accuracy Distribution
T
1
CH1 2.00V
BW CH2 2.00V BWM 40.0ns A CH1
5.76V
TPC 3. Driver Transition Waveforms Using MOSFETs of Figure 3
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THEORY OF OPERATION
The ADP3170 uses a current-mode, constant off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous buck topology. Constant off-time operation offers several performance advantages, including that no slope compensation is required for stable operation. A unique feature of the constant off-time control technique is that since the offtime is fixed, the converter's switching frequency is a function of the ratio of input voltage to output voltage. The fixed offtime is programmed by the value of an external capacitor connected to the CT pin. The on-time varies in such a way that a regulated output voltage is maintained as described below in the cycle-by-cycle operation. Under fixed operating conditions the on-time does not vary, and it varies only slightly as a function of load. This means that switching frequency is fairly constant in standard VRM applications.
Active Voltage Positioning
The output of the latch forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold, thus tracking the load current. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high.
Output Crowbar
The output voltage is sensed at the CS- pin. A voltage error amplifier, (gm), amplifies the difference between the output voltage and a programmable reference voltage. The reference voltage is programmed to between 1.05 V and 1.825 V by an internal 5-bit DAC, which reads the code at the voltage identification (VID) pins. (Refer to Table I for output voltage vs. VID pin code information.) A unique supplemental regulation technique called Analog Devices Optimal Positioning Technology (ADOPT) adjusts the output voltage as a function of the load current so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning, sometimes recommended for use with other architectures, has poor dynamic performance that renders it ineffective under the stringent repetitive transient conditions specified in Intel VRM documents. Consequently, such techniques do not allow the minimum possible number of output capacitors to be used. ADOPT, as used in the ADP3170, provides a bandwidth for transient response that is limited only by parasitic output inductance. This yields optimal load transient response with the minimum number of output capacitors.
Reference Output
An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 20% greater than the targeted value, the ADP3170 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 1.5 V, but is pulled up to 1.85 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than 0.75 V, the crowbar will release, allowing the output voltage to recover to 1.5 V if the fault condition has been removed.
Onboard Linear Regulator Controller
A 3.0 V reference is available on the ADP3170. This reference is normally used to accurately set the voltage positioning using a resistor divider to the COMP pin. In addition, the reference can be used for other functions such as generating a regulated voltage with an external amplifier. The reference is bypassed with a 1 nF capacitor to ground. It is not intended to drive larger capacitive loads, and it should not be used to provide more than 300 A of output current.
Cycle-by-Cycle Operation
The ADP3170 includes a linear regulator controller to provide a low cost solution for generating an additional supply rail. This regulator is internally set to 1.8 V with 2.8% accuracy. The output voltage is sensed by the high input impedance LRFB pin and compared to an internal fixed reference. The LRDRV pin controls the gate of an external N-channel MOSFET resulting in a negative feedback loop. The only additional components required are a capacitor and resistor for stability. Higher output voltages can be generated by placing a resistor divider between the linear regulator output and its LRFB pin. The maximum output load current is determined by the size and thermal impedance of the external power MOSFET that is placed in series with the supply and controlled by the ADP3170.
APPLICATION INFORMATION Specifications for a Design Example
The design parameters for a typical VRM 8.5-compliant Pentium III application (shown in Figure 3) are as follows: Input voltage: (VIN) = 5 V Auxiliary input: (VCC) = 12 V VID setting voltage: (VOUT) = 1.8 V Nominal output voltage at no load (VONL) = 1.845 V Nominal output voltage at maximum load (VOFL) = 1.771 V Static output voltage drop based on a 3.2 mW load line (ROUT) from no load to full load (V) = VONL - VOFL = 1.845 V - 1.771 V = 74 mV Maximum output current (IO[MAX]) = 23 A
During normal operation (when the output voltage is regulated), the voltage error amplifier and the current comparator are the main control elements. During the on-time of the high side MOSFET, the current comparator monitors the voltage between the CS+ and CS- pins. When the voltage level between the two pins reaches the threshold level, the DRVH output is switched to ground, which turns off the high side MOSFET. The timing capacitor CT is then charged at a rate determined by the off-time controller. While the timing capacitor is charging, the DRVL output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has charged to the upper threshold voltage level, a comparator resets a latch.
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CT Selection for Operating Frequency Table I. Output Voltage vs. VID Code
The ADP3170 uses a constant off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high-side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 0 V. During the off-time, CT is charged by a constant current of 150 A. Once CT reaches 3.0 V, a new on-time cycle is initiated. The value of the off-time is calculated using the continuous-mode operating frequency. Assuming a nominal operating frequency (fNOM) of 200 kHz at an output voltage of 1.8 V, the corresponding off-time is:
VID3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
VID2 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1
VID1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
VID0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID25 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOUT(NOM) 1.050 V 1.075 V 1.100 V 1.125 V 1.150 V 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V 1.425 V 1.450 V 1.475 V 1.500 V 1.525 V 1.550 V 1.575 V 1.600 V 1.625 V 1.650 V 1.675 V 1.700 V 1.725 V 1.750 V 1.775 V 1.800 V 1.825 V
V 1 tOFF = 1 - OUT x = VIN f NOM 1.8 V 1 1 - 5 V x 200 kHz = 3.2 s
(1)
The timing capacitor cab be calculated from the equation: CT = tOFF x I CT 3.2 s x 150 A = 150 pF 3V VT (TH ) (2)
The converter operates at the nominal operating frequency only at the above-specified VOUT and at light load. At higher values of VOUT, or under heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VOUT = 1.8 V is calculated to be 183 kHz (see Equation 3), where: RDS(ON)HSF is the resistance of the high-side MOSFET (estimated value: 6 m) R DS(ON)LSF is the resistance of the low-side MOSFET (estimated value: 6 m) RSENSE is the resistance of the sense resistor (estimated value: 2.5 m) RL is the resistance of the inductor (estimated value: 3 m)
f MIN =
1 tOFF
x
VIN - IO ( MAX ) x (RDS ( ON )HSF + RSENSE + RL - RDS ( ON )LSF )
VIN - IO ( MAX ) x (RDS ( ON )HSF + RSENSE + RL ) - VOUT
=
(3)
1 5V - 23 A x (6 m + 3 m ) - 1.8 V x = 183 kHz 3.3 s 5V - 23 A x (6 m + 2.5 m + 3 m - 6 m) )
Inductance Selection
The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs, but allows using smaller-size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger-size inductors and more output capacitance for the same peak-to-peak transient deviation. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor and input and output voltages: L= VOUT x tOFF I L ( RIPPLE ) (4)
For 6 A peak-to-peak ripple current, which corresponds to approximately 25% of the 23 A full-load dc current in an inductor, Equation 4 yields an inductance of:
L=
1.8 V x 3.3 s = 990 nH 6A
A 1 H inductor can be used, which gives a calculated ripple current of 5.9 A at no load. The inductor should not saturate at the peak current of 26 A and should be able to handle the sum of the power dissipation caused by the average current of 23 A in the winding and the core loss.
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Designing an Inductor
Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-M(R) from Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. Two main core types can be used in this application. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor. Closed-loop types,
L1 1.7 H 5V D1 MBR052LT1 12V C6 4.7nF 5V SB D2 MBR052LT1 FROM CPU C7 100nF
1 2 3 4 5 6 7
such as pot cores, PQ, U, and E cores, or toroids, cost more, but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape. There are many useful references for quickly designing a power inductor. Table II gives some examples.
Table II. Magnetics Design References
Magnetic Designer Software Intusoft (http://www.intusoft.com) Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-08
C1 1000 F
C2 1000 F
C3 1000 F U1
C4 1000 F
C5 1000 F C12 22 F Q1 FDB7045L L1 R6 1H 2.5m 1000 F 8 RUBYCON ZA SERIES 24m ESR (EACH)
ADP3170
VID3 VID2 VID1 VID0 VID25 PWRGD REF SD FB CS- GND 20 PGND 19 DRVH 18 DRVL 17 VCC 16 LRFB 15 LRDRV 14 COMP 13 CT 12 CS+ 11 C19 150pF
Q2 FDB7045L
VCC(CORE) 1.05V - 1.825V 23A VCC(CORE) RTN
C13 C14 C15 C16 C17 C18 C19 C20
C22 68pF COC 2.7nF RB 30.1k 1% 5V SB RA 13.7k 1% Q6 IRL3103 R7 10k C21 1F 1.8V SB 1.8V, 200mA C11 1nF R4 220 R5 220 C23 220 F
VTT PWRGD CLK
8 9 10
R1 1k C8 100pF
CORE PWRGD TO CPU
Figure 3. 24 A VRM 8.5-Compliant CPU Supply
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Selecting a Standard Inductor Output Resistance
The companies listed in Table III can provide design consultation and deliver power inductors optimized for high power applications upon request.
Table III. Power Inductor Manufacturers
Intel's VRM 8.5 specification requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc output resistance of:
ROUT = VONL - VOFL 1.845 V - 1.771V = = 3.2 m IO 23 A
Coilcraft (847) 639-6400 http://www.coilcraft.com Coiltronics (561) 752-5000 http://www.coiltronics.com Sumida Electric Company (408) 982-9660 http://www.sumida.com
RSENSE
(9)
The required dc output resistance can be achieved by terminating the gm amplifier with a resistor. The value of the total termination resistance that will yield the correct dc output resistance is:
RT = nI x RSENSE 25 x 2.5 m = = 8.88 k gm x ROUT 2.2 mmho x 3.2 m
(10)
where nI is the division ratio from the output voltage signal of the gm amplifier to the PWM comparator and gm is the transconductance of the gm amplifier itself.
Output Offset
The value of RSENSE is based on the required maximum output current. The current comparator of the ADP3170 has a minimum threshold of 69 mV. Note that this minimum value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and transients. The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO(MAX), which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE allowing a 20% margin for overhead and using the minimum current sense threshold of 69 mV yields:
RSENSE = VCS (TH )( MIN ) 69 mV = = 2.66 m (5) I RIPPLE 5.9 A IO ( MAX ) + 23 A + 2 2
In this case, 2.5 m was chosen, assuming two 5 m, 1 W resistors in parallel (for power dissipation reasons). Once RSENSE has been chosen, the output current at the point where current limit is reached, IOUT(CL), can be calculated using the maximum current sense threshold of 87 mV:
Intel's VRM 8.5 specification requires that at no load the output voltage of the regulator module be offset to a higher value than the nominal voltage corresponding to the VID code. The offset is introduced by realizing the total termination resistance of the gm amplifier with a divider connected between the REF pin and ground. The resistive divider introduces an offset to the output of the gm amplifier that, when reflected back through the gain of the gm stage, accurately positions the output voltage near its allowed maximum at light load. Furthermore, the output of the gm amplifier sets the current sense threshold voltage. At no load, the current sense threshold is increased by the peak of the ripple current in the inductor and reduced by the delay between sensing when the current threshold has been reached and when the high side MOSFET actually turns off. These two factors are combined with the inherent voltage (VGNL0), at the output of the gm amplifier that commands a current sense threshold of 0 mV:
VGNL = VONL +
I L ( RIPPLE ) x ROUT x nI 2
(11)
IOUT ( CL ) = IOUT ( CL )
VCS (TH )( MAX ) I L ( RIPPLE ) - RSENSE 2 87 mV 5.9 A = - = 31.6 A 2.5 m 2
(6)
At output voltages below 450 mV, the current sense threshold is reduced to 54 mV, and the ripple current is negligible. Therefore, the worst-case dead short output current is reduced to:
VIN - VOUT x t D x RSENSE x nI L 5.9 A x 3.2 m x 25 VGNL = 1V + - 2 5 V - 1.8 V x 60 ns x 2.5 m x 25 = 1.224 V 1 H
IOUT ( SC ) =
VCS ( SC ) 54 mV = = 21.6 A RSENSE 2.5 m
(7)
The divider resistors (RA for the upper, and RB for the lower) can now be calculated assuming that the internal resistance of the gm amplifier (ROGM) is 130 k:
VREF VREF - VGNL - gm x V + (12) RT 3V RB = = 29.7 k 3 V - 1.224 V - 2.2 mmho x 45 mV 8.88 k RB =
To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least:
PRSENSE = IO x RSENSE = 23 A2 x 2.5 m = 1.33 W
2
(8)
Choosing the nearest 1% resistor value gives RB = 30.1 k. Finally, RA is calculated:
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RA = 1 1 - - RT ROGM RB 1 = 12.83 k RA = 1 1 1 - - 8.88 k 1 M 29.7 k
COUT Selection
1 1
(13)
The optimal implementation of voltage positioning, ADOPT, will create an output impedance of the power converter that is entirely resistive over the widest possible frequency range, including dc, and equal to the specified dc output resistance. With the wide-band resistive output impedance the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output capacitor. With an ideal current-mode controlled converter, where the inductor current would respond without delay to the command signal, the resistive output impedance could be achieved by having a single-pole roll-off of the voltage gain of the voltageerror amplifier. The pole frequency must coincide with the ESR zero of the output capacitor. The ADP3170 uses peak-current control, which is known to have a nonideal, frequency-dependent command signal-toinductor current transfer function. The frequency dependence manifests in the form of a pair of complex conjugate poles at one-half of the switching frequency. A purely resistive output impedance could be achieved by canceling the complex conjugate with zeros at the same complex frequencies and adding a third pole equal to the ESR zero of the output capacitor. Such a compensating network would be quite complicated. Fortunately, in practice, it is sufficient to cancel the pair of complex conjugate poles with a single real zero placed at one-half of the switching frequency. Although the end result is not a perfectly resistive output impedance, the remaining frequency dependence causes only a slight percentage of deviation from the ideal resistive response. The single-pole and single-zero compensation can be easily implemented by terminating the gm error amplifier with the parallel combination of a resistor (RT) and a series RC network. The value of the terminating resistor RT was determined previously; the capacitance and resistance of the series RC network are calculated as follows:
COC = COC COUT x ESR RT 8 mF x 3 m = = 2.7 nF 8.88 k
Choosing the nearest 1% resistor value gives RA = 12.7 k. The required equivalent series resistance (ESR) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR of the output filter capacitor bank must be equal to or less than the specified output resistance of the voltage regulator (3.2 m). The capacitance must be large enough that the voltage across the capacitor, which is the sum of the resistive and capacitive voltage drops, does not move below or above the initial resistive step while the inductor current ramps up or down to the value corresponding to the new load current. One can use, for example, eight ZA series capacitors from Rubycon, which have a maximum ESR of 24 m. These eight 1000 F capacitors would give an ESR of 3 m. As long as the capacitance of the output capacitor is above a critical value, and the regulating loop is compensated with Analog Devices' proprietary compensation technique (ADOPT), the actual value has no influence on the peak-to-peak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows: IO (14) COUT ( CRIT ) = xL ROUT x (VOUT + V -)
COUT ( CRIT ) =
23 A x 1 H = 4.06 mF 3.2 m x (1.8 V + [-29 mV ])
The equivalent capacitance of the eight ZA series Rubycon capacitors is 8 x 1 mF = 8 mF. In this case, the total capacitance is safely above the critical value.
Feedback Loop Compensation Design for ADOPT
Optimized compensation of the ADP3170 allows the best possible containment of the peak-to-peak output voltage deviation. The output current slew rate of any practical switching power converter is inherently limited by the inductor to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors, and assuming that the capacitance of the output capacitor is larger than the critical value defined by Equation 14, this will produce a peak output voltage deviation equal to the ESR of the output capacitor times the load current change.
(15)
The closest standard value is 2.7 nF. The series resistance is:
2 COC x x f MIN 2 RZ = = 1255 2.7 nF x x 188 kHz RZ =
(16)
The nearest standard 5% resistor value is 1.2 k. Note that this resistor is only required when COUT approaches CCRIT (within 25% or less). In this example, COUT >> CCRIT, and RZ can therefore be omitted.
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ADP3170
Power MOSFETs
Two external N-channel power MOSFETs must be selected for use with the ADP3170, one for the main switch and one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)), the ON-resistance (RDS(ON)), and the gate charge (QG). Logic-level MOSFETs are highly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum value of VCC should be used. The maximum output current IO(MAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3170 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. For VIN = 5 V and VOUT = 1.8 V, the maximum duty ratio of the high-side FET is:
higher efficiency, but increase the system cost. A Fairchild FDB7045L (RDS(ON) = 4.5 m nominal, 6 m worst-case) is a good choice for both the low-side and high-side MOSFET. With this choice, the high-side MOSFET dissipation is:
PHSF = RDS (ON )HSF x I HSF ( MAX ) + VIN x QRR x f MIN PHSF 5 x 28.6 A x 50 nC x 183 kHz = 6 m x 14.7 A2 + + 2 x1A
2
VIN x I L ( PEAK ) x QG x f MIN + 2 x IG
(24)
5 V x 100 nC x 183 kHz = 2.04 W
DHSF ( MAX ) = 1 - ( f MIN x tOFF ) DHSF ( MAX ) = 1 - (183 kHz x 3.3 s ) = 40%
(17)
The maximum duty ratio of the low-side (synchronous rectifier) MOSFET is:
DLSF ( MAX ) = 1 - DHSF ( MAX ) = 60%
The maximum rms current of the high-side MOSFET is:
I HSF ( MAX ) = DHSF ( MAX ) x
2
(18)
where the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. In the second term, QG is the gate charge to be removed from the gate for turnoff and IG is the gate turn-off current. From the data sheet, the value of QG for the FDB7045L is 50 nC and the peak gate drive current provided by the ADP3170 is about 1 A. In the third term, QRR is the charge stored in the body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDB7045L does not give that information, so an estimated value of 100 nC is used. The estimate is based on information found on the data sheets of similar devices. The low-side MOSFET dissipation is:
I L (VALLEY ) + I L (VALLEY ) x I L ( PEAK ) + vI L ( PEAK ) 3
2
2
(
)
2
(19)
I HSF ( MAX ) = 0.4 x
17.4 A + (17.4 A x 28.6 A) + 28.6 A = 14.7 A 3
PLSF = RDS (ON )HSF x I HSF ( MAX ) PLSF = 6 m x 18 A2 = 1.94 W
2
(25)
The maximum rms current of the low-side MOSFET is:
I LSF (MAX ) = D LSF (MAX ) x I HSF (MAX ) = 0.6 x I L (VALLEY ) + I L (VALLEY ) x I L (PEAK ) + I L (PEAK )
2
Note that there are no switching losses in the low-side MOSFET. Surface mount MOSFETs are preferred in CPU core converter applications due to their ability to be handled by automatic assembly equipment. The TO-263 package offers the power handling of a TO-220 in a surface mount package. However, this package still needs adequate copper area on the PCB to help move the heat away from the package. The junction temperature for a given area of two-ounce copper can be approximated using:
(
)
2
17.4 A 2 + 17.4 A x 28.6 A + 28.6 A 2 3
(
)
3 = 18 A
(20)
The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation will be:
PD ( FETs ) = 0.1 x VOUT x IOUT ( MAX ) PD ( FETs ) = 0.1 x 1.8 V x 23 A = 4.1 W
(21) assuming: Allocating half of the total dissipation for the high-side MOSFET and half for the low-side MOSFET, and assuming that the resistive loss of the high-side MOSFET is one-third, and the switching loss is two-thirds of its portion, the required maximum MOSFET resistances will be:
TJ = ( JA x PD ) + TA
JA JA JA
(26)
= 45C/W for 0.5 in2 = 36C/W for 1 in2 = 28C/W for 2 in2
For 1 in 2 of copper area attached to each transistor and an ambient temperature of 50C:
RDS (ON )HSF =
PD ( FETS ) 3xI
2 HSF ( MAX )
=
4.1 W = 6 m (22) 3 x 14.7 A2
(23)
T JHSF = 28o C / W x 2.06W + 50o C = 108o C T JLSF
o o o
RDS (ON )LS =
PD ( FETS ) I LSF ( MAX )
2
4.1W = = 6 m 2 x 18 A2
( ) = (28 C / W x 1.94W ) + 50 C = 104 C
Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow
All of the above-calculated junction temperatures are safely below the 175C maximum specified junction temperature of the selected MOSFETs.
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ADP3170
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of the high-side MOSFET is a square wave with a duty ratio of VOUT/ VlN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: I C ( RMS ) = IO DHSF - DHSF
2
The corresponding power dissipation in the MOSFET, together with any resistance added in series from input to output is given by: PLDO = (VIN - VOUT ) x IOUT (30)
I C ( RMS ) = 23 A x 0.4 - 0.42 = 11.3 A
(27)
Minimum power dissipation and maximum efficiency are accomplished by choosing the lowest available input voltage that exceeds the desired output voltage. However, if the chosen input source is itself generated by a linear regulator, its power dissipation will be increased in proportion to the additional current it must now provide.
1F RS 250m 3.3V
For a ZA-type capacitor with 1000 F capacitance and 6.3 V voltage rating, the ESR is 24 m and the maximum allowable ripple current at 100 kHz is 2 A. At 105C, at least six such capacitors must be connected in parallel to handle the calculated ripple current. At 50C ambient, however, a higher ripple current can be tolerated, so five capacitors in parallel are adequate. The ripple voltage across the five paralleled capacitors is:
ESRC DHSF ( MAX ) VC ( RIPPLE ) = IO x + nC x CIN x f MIN nC 24 m 0.4 VC ( RIPPLE ) = 23 A x x = 120 mV 5 x 1 mF x 183 kHz 5
ADP3170
VLR 1.8V, 2.2A 1k 68pF 100 F 10k 1.8V LRDRV
LRFB
(28)
Figure 4. Adding Overcurrent Protection to the Linear Regulator
Implementing Current Limit for the Linear Regulators
To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/ms, an additional small inductor (L > 1 H @ 10 A) should be inserted between the converter and the supply bus.
Linear Regulators
The circuit of Figure 4 gives an example of a current limit protection circuit that can be used in conjunction with the linear regulator. The output voltage is internally set by the LRFB pin. The value of the current sense resistor may be calculated as follows: RS 540m V 540m V = = 250 m IO ( MAX ) 2.2 A (31)
The linear regulator provides a low cost, convenient and versatile solution for generating a 1.8 V supply rail. The maximum output load current is determined by the size and thermal impedance of the external N-channel power MOSFET that is placed in series with the supply and controlled by the ADP3170. The output voltage is sensed at the LRFB pin and compared to an internal reference voltage in a negative feedback loop which keeps the output voltage in regulation. If the load is reduced or increased, the MOSFET drive will also be reduced or increased by the ADP3170 to provide a well regulated output voltage. Output voltages higher than the fixed internal reference voltage can be programmed by adding an external resistor divider.
Efficiency of the Linear Regulators
The power rating of the current sense resistor must be at least:
PD ( RS ) = RS x IO ( MAX ) = 1.2 W
2
(32)
The maximum linear regulator MOSFET junction temperature with a shorted output is:
TJ( MAX ) = TA + JC x VIN x IO( MAX )
(
TJ( MAX ) = 50o C + 1.4o C / W x 3.3 V x 2.2 A = 60o C
(
)
)
(33)
The efficiency and corresponding power dissipation of each of the linear regulators are not determined by the ADP3170. Rather, these are a function of input and output voltage and load current. Efficiency is approximated by the formula:
which is within the maximum allowed by the MOSFET's data sheet specification. The maximum MOSFET junction temperature at nominal output is: TJ( NOM ) = 50o C + JC x VIN - VOUT x IO( NOM )
(
= 100% x
VOUT VIN
(29)
TJ( NOM ) = 50o C + 1.4o C / W x 3.3 V - 1.8 V x 2 A = 54o C This example assumes an infinite heat sink. The practical limitation will be based on the actual heat sink used.
(
[
[
]
]
)
)
(34)
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ADP3170
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal performance of a switching regulator in a PC system:
General Recommendations
1.
For best results, a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the voltage and current sense lines of the ADP3170) must cross through power circuitry, it is best if a ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. The GND pin of the ADP3170 should connect first to a ceramic bypass capacitor (on the VCC pin) and then into the analog ground plane. The analog ground plane should be located below the ADP3170 and the surrounding smallsignal components, such as, the timing capacitor and compensation network. The analog ground plane should connect to power ground plane at a single point; the best location being the negative terminal of the last output capacitor. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors too should be distributed, and generally in proportion to where the load tends to be more dynamic. It is advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). Absolutely avoid crossing any signal lines over the switching power path loop, described below.
2.
3.
upper MOSFET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body-drain diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET's body-drain diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 9. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path); and improved thermal performance-- especially if the vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air.
4.
10. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors. 11. For best EMI containment, the ground plane should extend fully under all the power components. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, the current sense resistor, any snubbing elements that might be added to dampen ringing and the output capacitors.
Signal Circuitry
5.
6.
Power Circuitry
7. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system, as well as, noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs and the power Schottky diode, if used, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing; and it accommodates the high current demand with minimal voltage loss. 8. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower MOSFET's source (anode) to drain (cathode) will help to minimize switching power dissipation in the
12. The output voltage is sensed and regulated between the GND pin (which connects to the signal ground plane) and the CS- pin. The output current is sensed (as a voltage) and regulated between the CS- pin and the CS+ pin. In order to avoid differential mode noise pickup in those sensed signals, their loop areas should be small. Thus the CS- trace should be routed atop the signal ground plane, and the CS+ and CS- traces should be routed as a closely coupled pair (CS+ should be over the signal ground plane as well). 13. The CS+ and CS- traces should be Kelvin connected to the current sense resistor so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. It is desirable to have the ADP3170 close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the GND pin is minimized, and voltage regulation is not compromised.
-14-
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ADP3170
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead TSSOP (RU-20)
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
REV. 0
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C02620-1.5-7/01(0)
PRINTED IN U.S.A.

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